Code: A-27                                                                Subject: DIGITAL HARDWARE DESIGN

Time: 3 Hours                                                                                                     Max. Marks: 100

 

NOTE: There are 11 Questions in all.

·      Question 1 is compulsory and carries 16 marks. Answer to Q. 1. must be written in the space provided for it in the answer book supplied and nowhere else.

·      Answer any THREE Questions each from Part I and Part II. Each of these questions carries 14 marks.

·      Any required data not explicitly given, may be suitably assumed and stated.

 

Q.1       Choose the correct or best alternative in the following:                                           (2x8)

 

a.       In an FPLA

 

                   (A)  only OR plane is programmable.  

                   (B)  only AND plane is programmable.

(C)     both AND & OR planes are programmable.

(D) none of the planes are programmable

       

b.      Which of the following is a unate function?

                                                                                                                                                   

                   (A) .                               (B)  g = xy + wz.

                   (C)  .                             (D) .

 

             c.   Initially the contents of a 4-bit shift register are 1101.  The shift register is shifted six times to the right with serial inputs being 101101.  What are the contents of the shift register after six right shift operations?

 

                   (A)  101011.                                       (B)  101010.

                   (C)  110101.                                       (D)  101101.

 

             d.   For the following output sequences

                   O1 = 1010d110d0

                   O2 = 10d0d11dd0

                   O3 = 1d0d011110

 

(A)  O1 and O2 are not compatible.    (B)  O1 and O3 are not compatible.

(C)  O3 and O2 are not compatible.    (D)  none of the above.

       

             e.   The storage cells in the LUTs of an FPGA are

 

(A) volatile.                                         (B) non-volatile.

                   (C) same as CPLD blocks.                  (D) none of the above.

 

             f.    The Boolean expression  can be reduced to

                  

(A) ab + bc + ac.                                (B) .

                   (C) .                                        (D) .

             g.   The circuit shown in Fig.1 is

 
       

 

 

 

 

 

 

 

 

 

 

            

 

 

 

                   (A) Mod-7 counter.                            

                   (B) Mod-5 counter.

(C) Mod-4 counter.                            

(D) shift register.
 
 


             h.   The circuit shown in Fig.2

                   detects the following sequence

 

 

                   (A)  101.                                            

                   (B)  011.                                                                 

(C)  111.                          

(D)  110.

 

 

PART I

Answer any THREE Questions. Each question carries 14 marks.

 

  Q.2     a.   What do you mean by functional decomposition?  What is disjunctive decomposition?                    (4)

 

             b.   Define symmetric function with the help of an example.                                        (4)

 

             c.   The function

                    

                   can be decomposed to form . 

                   Determine the functions F and g.                                                                        (6)          

                  

  Q.3     a.   Minimize the following function using the Quine McCluskey method .                                        (9)

 

             b.   What is functionally complete logic gate?  Show that NAND and NOR gates are functionally complete gates.                                                           (5)

            


  Q.4     a.   Derive the logic equations for carry look ahead adder for a 4-bit parallel adder and show its implementation using ROM.                                         (7)

 

             b.   Implement a full subtractor circuit using an appropriate multiplexer.                      (7)

                  

  Q.5     a.   Draw a basic PAL circuit having four inputs, eight product terms and one active high combinational output.  Draw fuses on your diagram for implementation of binary to excess-3 code converter.        (7)

       

             b.   Design a synchronous mod-7 counter using D flipflops.                                       (7)

       

  Q.6           A sequential network has one output and one input.  The output should be 1 if the input sequence ends in either 010 or 1001 and should be 0 otherwise.  Find the Mealy flow graph and state table.  Minimize the state table, and realize it using D flipflops.                                                         (14)

 

            

PART II

Answer any THREE Questions. Each question carries 14 marks.

 

  Q.7     a.   What is an incompletely specified machine?  Find the reduced state table for the incompletely specified machine given below:                           (10)

            

PS

(Present State)

NS, Z (Next State, Output)

I1

(Input 1)

I2

(Input 2)

A

B, 0

C, 1

B

D, 0

C, 1

C

A, 0

E, 0

D

-, -

F, 1

E

G, 1

F, 0

F

D, 1

-, -

G

D, 0

E, 0

 

             b.   Explain the following terms:                 

                   (i)  Maximal compatibles.                     (ii)  Closed covering.                               (4)

 

  Q.8     a.   State the difference between Mealy and Moore machines with the help of a suitable example.                                                                    (6)

            

             b.   Convert the following Mealy machine to an equivalent Moore machine.      (8)                  

                  

PS

(Present State)

NS, Z (Next State, Output)

x=0

x=1

A

C, 0

B, 0

B

A, 1

D, 0

C

B, 1

A, 1

D

D, 1

C, 0

 

       


Q.9   a.        Find a state assignment for the following machine which reduces the inter-dependency of the state variables.                                        (8)

                                                                             

PS

(Present State)

NS (Next State)

x=0

x=1

A

E

B

B

E

A

C

D

A

D

C

F

E

F

C

F

E

C

 

             b.   Draw an ASM chart for a binary multiplier and design the control logic using one hot approach.                                                                 (6)

            

Q.10           a.                                                        Write a VHDL program for a full adder and use this as a package to write VHDL code for a 4-bit parallel adder.                                                       (8)

            

             b.   Write VHDL code for a 4-bit shift register in behavioural style of modelling.                       (6)

       

Q.11                                                                      Write short notes on any TWO of the following:

 

(i)    FPGA.

(ii)         Microprogram control unit.      

(iii)       Data Flow style of modelling.                                                      (2 x 7 = 14)