Code: A-27                                                                Subject: DIGITAL HARDWARE DESIGN

Time: 3 Hours                                                                                                      Max. Marks: 100

NOTE: There are 9 Questions in all.

· Question 1 is compulsory and carries 20 marks. Answer to Q. 1. must be written in the space provided for it in the answer book supplied and nowhere else.

· Out of the remaining EIGHT Questions answer any FIVE Questions. Each question carries 16 marks.

· Any required data not explicitly given, may be suitably assumed and stated.

Q.1       Choose the correct or best alternative in the following:                                         (2x10)

a. The threshold element shown in Fig. 1 realises the switching function 

(A) .                 

                   (B) .

(C) .                    

(D) .

b. A pulse mode asynchronous circuit is having 2 levels of excitation logic with propagation delay of 5 ns each and a latch with delay of 10 ns.  Minimum input pulse width required for the circuit is 

(A)  5 ns                                             (B)  10 ns

(C)  15 ns                                            (D)  20 ns

             c.   A mealy machine is

(A) level input pulse output machine.  

(B) pulse input level output machine.

(C) pulse input pulse output machine. 

(D) level input level output machine.

             d.   In Moore machine, output is a function of

(A)  present state and external inputs.

(B)  only present state.

(C)  only external inputs.

(D)  neither present state nor external inputs.        

             e.   Which of the following is a unate function

(A) (B) 

(C)  (D)

             f.    Fig. 2 is block diagram of a multiplier that multiplies two-bit binary numbers.  How many output variables (x) are needed for it

(A) 2                                                 

(B) 4

(C) 6                                                 

(D) 8

             g.   The circuit shown in Fig. 3 is a

(A) 2-bit up down counter.                

(B) 4-bit up down counter.

(C) 4-bit ring counter.                        

(D) 4-bit Johnson counter.

             h.   Time  and  shown in Fig.4 respectively represent

(A) set up and hold time.                    

(B) hold and set up time.

(C) rise and fall time.                          

(D) fall and rise time.

             i.    Canonical sum of product form for the function  is

(A) .                      (B) .

(C) .                      (D) .

             j.    An n-bit Johnson counter generates a counting sequence of length

(A)  .                                             (B) 2 n.

(C)  4 n.                                              (D) n.

Answer any FIVE Questions out of EIGHT Questions.

Each question carries 16 marks.

Q.2     a.   Derive a minimum-cost realisation of a four-variable function that is equal to 1 if exactly two or exactly three of its variables are equal to 1, otherwise it is equal to 0.                                                      (6)

             b.   A circuit with two outputs has to implement the following functions:

                   Design a minimum-cost circuit to complement the above function. Compare its cost with combined costs of two circuits that implement the functions f and g separately.  Assume that inputs are available in both uncomplemented and complemented form.                                                       (10)

Q.3     a.   The function  can be decomposed to the form .  Determine the function F and .                   (6)

             b.   Design a single digit BCD adder using an EPROM.  Determine the minimum size (mxn bits) of the EPROM.                                                           (10)

Q.4     a.   Explain with the help of a suitable logic diagram the differences between a registered PAL and a GAL.                                                                   (6)

b.   Write a VHDL program for a multiplexer.                                                   (4)

             c.   Write a VHDL program for a 4 bit shift register.                                                 (6)

Q.5           The output z of a fundamental, two-input sequential circuit changes from 0 to 1 only when changes from 0 to 1 while .  Further, the output changes from 1 to 0 only when  changes from 1 to 0 while =0.

(i)   Find a minimum row reduced flow table.                                                      (8)

(ii)  Show a valid assignment and write a set of hazard free excitation and output equations.             (8)

  Q.6     a. Reduce the state table given below using equivalence class state reduction technique.                      (8)

Present State (PS)	Next State (NS), Output (Z)
	x=0	x=1

             b.   Construct a Mealy state diagram that detects a serial input sequence of 10110. Overlapping of the patterns is possible.  When the input pattern is detected, it causes output z to be asserted high.  First write the flow table and then reduce it.                                                                                            (8)

Q.7     a.   Find the reduced state table for the machine M given below:                               (8)

PS	NS,
	xy=00	xy=01	xy=10	xy=11
A	A, -	C, 1	E, 1	B, 1
B	E, 0	C, -	-, -	-, -
C	F, 0	F, 1	E, 0	-, -
D	-, -	E, 0	A, -	-, -
E	-, -	-, -	A, 0	D, 1
F	C, 0	-, -	B, 0	C, 1

Machine M

b.   What is maximal compatibility?  What is the difference between compatible states and maximal compatibility?                                                           (8)

Q.8     a.   For the two given Machines and , find a bigger machine M which is a serial combination of  and .                                                   (8)

	NS,Z		PS	NS,Z
PS	x=0	x=1		y=0	y=1
A	B, 0	C, 0	a	a, 0	b, 1
B	A, 1	C, 0	b	b, 1	a, 1
C	B, 1	A, 0

Machine M1                                                    Machine M2

             b.   Find the state assignment, by choosing self dependent subset, for the machine given below:             (8)

PS	NS		Z
	x=0	x=1
A	E	B	1
B	E	A	0
C	D	A	0
D	C	F	1
E	F	C	0
F	E	C	0

Q.9     a.   Write ASM chart for a machine which scans a 3 bit word and produces an output  when last two bits in consecutive 3 bit word are ones and second output  which identifies the start of each 3-bit word.  Implement the machine using multiplexers.                                                                          (6)

b.   Explain the role of CAD Tools in digital system design.                                       (6)

c.   Write a brief note on a micro-programmed controller.                                         (4)