DE09 DIGITAL ELECTRONICS
1.1
Introduction.
1.2
Number
Systems.
1.3
Binary
Number System, Conversion from binary-to-decimal and decimal-to-binary
numbers.
1.4
Binary
Arithmetic (addition/subtraction), Signed Numbers (sign magnitude, 1’s
complement and 2‘s complement representation).
1.5
Octal
Number System, Conversion to/from Binary, Octal Arithmetic.
1.6
Hexadecimal
Number System, Conversion to/from Binary, Arithmetic.
1.7
Codes-BCD,
Excess-3, Gray, Octal, Hexadecimal and Alphanumeric.
1.8
Error
Codes.
2.1
Introduction.
2.2
Boolean
Algebra: Laws, Postulates, Theorems.
2.3
Logic
Gates: AND, OR, NOT, NAND, NOR, Ex-OR.
2.4
Boolean
functions, Standard Canonical Forms, Realization with gates.
2.5
Karnaugh
map representation of Logical Functions.
2.6
Simplification
of Logic Functions using K-maps.
2.7
Simplification
Functions specified in Minterms/Maxterms.
2.8
Simplification
Functions not specified in Minterms/Maxterms.
2.9
Don’t
Care Conditions.
2.10
Design
Examples.
2.11
Characteristics
of Digital ICs: speed of operation, power dissipation, fanout, current/voltage levels, noise immunity,
operating temperature, power supply.
2.12
Digital
Logic Families: RTL (logic operation, loading considerations, noise margins,
propagation delay time).
2.13
Direct
Coupled Transistor Logic.
2.14
Diode
Transistor Logic: NAND gate operation, propagation delays, wired logic.
Modified DTL NAND Gate.
2.15
Transistor
Transistor Logic: NAND gate operation, clamping diodes.
2.16
Field
Effect Transistors: JFET, enhancement and depletion MOSFETs, switching
characteristics.
2.17
Digital
Logic Families: MOS and CMOS: MOSFET NAND/NOR gates, propagation delay times,
power dissipation.
2.18
CMOS
Logic: CMOS invertor, CMOS transmission gate.
2.19
Wired-AND
and Open Collector Gates.
2.20
Tristate
Gates.
2.21
Interfacing
CMOS and TTL.
I [1 (1.1, 1.3-1.6), 3
(3.7), 4 (4.2-4.4, 4.6-4.8, 4.13-4.15, 4.17) 5 (5.1-5.8)]
3.1
Multiplexers.
3.2
Combinational
Logic Design using Multiplexers.
3.3
Multiplexer
Tree.
3.4
Demultiplexers/Decoders
and their Use in Combinational Logic Design.
4.1
Half
Adders/Subtractors, Full Adders/Subtractors.
4.2
Adders,
Cascading of Adders and their Use as Subtractors.
4.3
BCD
Adders/Subtractors.
4.4
Digital
Comparators.
4.5
Parity
Generator/Checkers.
4.6
Code
Converters: BCD to binary, binary to BCD.
4.7
Priority
Encoders: decimal to BCD, octal to binary .
4.8
Decoders/Drivers
for Display Devices (Common Anode/Cathode): BCD to decimal, BCD to
seven-segment.
5.1
Introduction.
5.2
1-bit
Memory Cell.
5.3
Clocked
S-R Flip Flop, Preset and Clear.
5.4
J-K
Flip Flop, Race Around Condition, Master-Slave Flip Flop.
5.5
D
Flip Flops.
5.6
T
Flip Flops.
5.7
Excitation
Table of FF, Design of a Clocked FF.
5.8
Edge
Triggered Flip Flop.
5.9
Bounce
Elimination.
5.10 Shift
Registers: SISO, PIPO, SIPO, PISO, bi-directional registers, ring counters and
twisted ring counters, sequence generator.
5.11 Asynchronous Counters: up-down counters, mod-N counters, ICs.
5.12 Synchronous
Counters: design, lock out, ICs, cascading of counters.
6.1
Memory
Organization, Read Operation, Write Operation.
6.2
Expanding
Memory Size: expanding word size and word capacity.
6.3
Memories:
principle of operation.
6.4
ROM,
PROM, EPROM; organization, programming mechanisms.
6.5
Read
Write Memories: bipolar cell, MOS RAMs (static and dynamic).
7.1
Introduction.
7.2
D/A
Converters, Weighted Resistance D/A Converters.
7.3
R-2R
Ladder D/A Converter.
7.4
Specifications
for D/A Converters.
7.5
An
Example (input code, output, calibration/adjustments).
7.6
Analog
to Digital Converters- Quantization and Error.
7.7
Parallel
Comparator A/D Converter.
7.8
Successive
Approximation A/D Converter.
7.9
Counting
type A/D Converter.
7.10
Dual
Slope A/D Converter.
7.11
A/D
Converter using Voltage to Frequency Conversion.
7.12
A/D
Converter using Voltage to Time Conversion.
7.13
An
Example: operation, digital output, analog input, calibration.
Text Books
I. R.P.Jain, “Modern Digital Electronics”, Tata McGraw-Hill
Publishing Company Limited, 2nd Edition, New Delhi. 1997.